As the throughput demands of high-performance serial links are constantly growing, the need for robust low-power high-speed transceivers is increasing. A system-aware transceiver design approach shows great promise in addressing those issues. However, in order to fully exploit the benefits that modern digital error-correction techniques are offering, a new class of adaptive front-end receiver circuitry is needed. This research is investigating the power vs performance tradeoffs in CMOS PLL-based clock recovery units. The goal is to identify and design an optimal power-aware architecture, which would enable real-time adaptation to both link conditions and PVT variations, resulting in resilient, low-power, high-speed serial link systems.
As the clock rate of microprocessors keep increasing, high data rate IO links should be designed to realize their maximum benefit. However designing robust, low power high speed IO links is very challenging due to the increased transmission line loss, crosstalk, and signal distortion resulting in intersymbol interference. Synchronous sampling is often employed to overcome these challenges. However synchronous sampling makes use of a high purity oscillator to minimize the clock jitter. High purity oscillators used in typical high-speed IO links consume nearly 40% of the total power. This research focuses on the design and implementation of a reconfigurable voltage controlled oscillator whose performance can be altered in real time by the system to minimize the power consumption while achieving the required performance.
As semiconductor industry is struggling to keep up with the Moore's Law, integrated circuits are becoming smaller, faster and increasingly harder to design. Therefore, there is a constant demand for fast, accurate, and powerful CAD tools. Development of superior CAD tools, in turn, requires creation of fast, accurate, powerful, and computationally inexpensive numerical methods for modeling of integrated circuits. With process scaling the number of transistors on a chip is heading into billions, making the analysis of such structures with traditional methods virtually impossible. Our research focuses on the development of novel techniques for efficient simulation of very large networks. One of the proposed methods is the Latency Insertion Method (LIM). LIM is an efficient time-domain technique that takes advantage of inherent or artificial latency in a network to generate a time-stepping algorithm similar to the Yee algorithm used in the Finite-Difference Time-Domain Method. LIM is in fact a scalar version of FDTD adopted for circuit simulation; it has linear numerical complexity, low memory requirements, and enables simulation of networks with millions of nodes.
With the advent of the computer age, circuit simulators have become an invaluable tool in the design and development process of any electronic component. Circuit simulators provide developers with the ability to accurately predict the behavior of electronic devices before their actual constructions. This saves a lot of time and money as a design can be gradually tuned by simulating it on a computer before constructing the actual physical system. Thus, generating accurate representations of electronic components and interconnects for circuit simulators is of utmost importance in s world. One of the biggest challenges in circuit simulators is the ability to accurately predict the frequency dependent effects of interconnects and packages in a reasonable amount of time. This becomes more and more important as the operating frequencies of modern devices gets higher and higher, as these frequency dependent effects can no longer be overlooked. Blackbox or broadband macromodeling is the process of generating a robust model of passive interconnects and packages that captures these frequency dependent effects, such that they can be accurately accounted for in circuit simulators.
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