Power Delivery for Heterogeneously Integrated AI Systems
(co-PIs: Elyse Rosenbaum & Pavan Hanumolu, Coordinated Science Lab)
One challenge for AI systems is to integrate the broad array of elements needed to
efficiently solve the intended computing tasks. Multiple, and perhaps differing,
computing cores are needed to achieve the speed and power efficiency, memory elements
are needed to store the data, and communication circuits are needed to connect to the
computing network. To implement those diverse functions, a variety of chiplets are
designed and then integrated into a package. Once the chiplets are defined, a network of
signaling interfaces that are low-latency, low-power, and high-bandwidth are needed to
interconnect the devices. To achieve the desired performance, it is necessary to have
an efficient power delivery network, which delivers the proper voltage levels with high
efficiency and low noise to the chiplets and the circuits that connect the chiplets together.
The objective of this research project is to improve the efficiency of the power delivery
to the chiplets, including the interface circuits, to enable the heterogeneously integrated
devices to meet the desired performance objectives. The scope of research includes the design
and integration of the active power conversion circuits and the passive power delivery network,
including decoupling capacitors, to operate as an integrated unit. The optimization of that network
implementation is the desired research outcome.
Heterogeneous Integration for Neuromorphic Integrated Circuits
This project addresses the challenges related to the modeling and analysis of neuromorphic integrated systems. We assume that a chiplet approach to the design of the system will be adopted. The packaging and wiring of circuit components have serious impact on the reliability and stability of signal transmission in heterogeneous integrated systems. For instance, a good power distribution strategy should provide accurate and reliable methods for estimating power-bus/ground plane impedance and its variation with frequency. The approach should also provide methods for determining the location and value of bypass capacitors.
Mixed-Signal Analog Circuit Simulator for Multi-Scale Resolution
A critical void in state-of-the-art RF, and more broadly, analog circuit simulation is the availability of non-linear, transient simulation software capable of fast, accurate analysis of advanced, complex RF systems excited by waveforms of time-varying frequency content. Such an analysis is not possible with today’s commercially available time-domain and frequency-domain circuit simulators, the development of which over the past several decades has been primarily guided by their application for the computer-aided design of analog, digital, and mixed-signal circuits of predetermined specific functionality. These circuit simulators, while sufficiently accurate and effective at the rapid design iteration and prototyping of electronic components and circuits within their specified design specs, are unable to provide the detailed circuit response necessary for exploring, analyzing, and manipulating any extraordinary behavior that might occur when the circuit is excited by general time-frequency waveforms. In addition to the complex waveforms used in modern communication systems such as CDMA and 5G OFDM, the class of time-frequency waveforms includes pulsed ultra-wideband and non-periodic pulsed frequency waveforms. The latter are of significant interest to the design of low-probability-of-intercept (LPI) radar waveforms with applications to jamming and Electronic Warfare (EW).The objective of this project demonstrate that the latency insertion method (LIM) can address and resolve the hurdles of analog simulation, which, because of its dynamic topology and its simplicity, is the most natural method for capturing the dynamic behavior of a network.
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